US 2005/0017290 discloses an RC-IGBT, which includes, within one wafer, an insulated gate bipolar transistor (IGBT) with a built-in freewheeling diode. As shown in FIG. 1, such RC-IGBT 1 includes a first layer 2 formed as an n-type base layer with a first main side 21 and a second main side 22 opposite the first main side 21. A second p-type layer 3 is arranged on the first main side 21. On the second layer 3, a third n-type layer 4 with a higher doping than the first layer 2 is arranged on the first main side 21. The third layer 4 is surrounded by the second layer 3 in such a way that in the central part of the second layer 3, no portion of the third layer 4 is arranged above the second layer 3.
A fifth electrically insulating layer 6 is arranged on the first main side 21. The fifth layer 6 covers the second layer 3 and the first layer 2, and partially covers the third layer 4. An electrically conductive fourth layer 5 is completely embedded in the fifth layer 6. No portions of the fourth layer 5 or the fifth layer 6 are arranged above the central part of the second layer 3.
A first electrical contact 10 is arranged on the first main side 21 and covers the fifth layer 6. The first electrical contact 10 is in direct electrical contact with the second layer 3 and the third layer 4, but is electrically insulated from the fourth layer 5.
P-type sixth layers 7 and n-type seventh layers 8 are arranged alternately in a plane on the second main side 22. The seventh layers 8 have a higher doping than the n-type first layer 2. The seventh layers 8 are arranged directly below the second layer 3 and the first electrical contact 10 if seen in an orthographic projection.
A second electrical contact 11 is arranged on the second main side 22. The second electrical contact 11 covers the sixth and seventh layers 7, 8 and is in direct electrical contact with the sixth and seventh layers 7, 8.
In the RC-IGBT 1 illustrated in FIG. 1, a freewheeling diode is formed between the second electrical contact 11, part of which forms a cathode electrode in the diode, the seventh layer 8, which forms a cathode region in the diode, the first layer 2, part of which forms a base layer in the diode, the second layer 3, part of which forms an anode region in the diode, and the first electrical contact 10, which forms an anode in the diode.
An IGBT is formed between the second electrical contact 11, part of which forms a collector electrode in the IGBT, the sixth layer 7, which forms a collector region in the IGBT, the first layer 2, part of which forms a base layer, the second layer 3, part of which forms a p-base region in the IGBT, the third layer 4, which forms a source region in the IGBT, and the first electrical contact 10, which forms an emitter electrode. During an on-state of the IGBT, a channel is formed between the emitter electrode, the source region and the p-base region towards the n-base layer.
US 2005/0258493 discloses a similar RC-IGBT, but with a trench gate structure. A recombination layer is formed below the trench gate electrode and the p-base region. The recombination layer extends completely through the first layer in a plane parallel to the first main side, i.e. the recombination layer is formed through the diode section as well as through the IGBT section. This recombination layer is formed by uniform Helium irradiation. By the introduction of this layer, the plasma distribution in the diode section of the RC-IGBT is improved. Within the IGBT section, however, it is not desired to have reduced plasma distribution, because it leads to higher on-state losses.
JP 2007-103770 also discloses an RC-IGBT. The lifetime controlling is improved by introducing local recombination layers, which are arranged in the first layer in the diode section close to the second main side, i.e. in the area in which the second layer is in direct contact with the anode and the cathode layer on the second main side. The defect layer is formed by a complex masking technique, in which a metal mask is introduced on the second side of the wafer after the finishing of the device on the first side (emitter side in the finalized device) and after creating the collector and cathode layer and the second electrical contact. The mask has openings in the diode section, i.e. in the area in which the cathode layer is arranged. The mask has to be aligned to the first electrical contact on the first side of the wafer, i.e. with the side which lies opposite to the side where the mask is positioned. Only by such a positioning can it be ensured that the recombination fields will be arranged in the diode section of the reverse-conducting IGBT in the first base layer between the cathode layer and the anode layer. Then, the wafer is irradiated with a light ion beam. The thickness of the mask and/or energy of the beam are chosen in such a way that the ions only penetrate into the wafer in the diode section, i.e. in the part in which the collector layers are arranged. Afterwards, the mask is removed and the device is completed.
DE 102 61 424 B3 discloses a manufacturing method for an IGBT with a defect layer, which is arranged in the second layer. The defect layer has been manufactured previous to the finalizing of the electrically insulating layer, i.e. the defect layer has been manufactured after manufacturing of that part of the electrically insulating layer, which is located under the electrically conductive fourth layer, and after manufacturing of the electrically conductive fourth layer, but before finalizing the electrically insulating layer, i.e. before manufacturing that part of the insulating layer which covers the electrically conductive fourth layer 5 to the top and to that side, on which the poly opening is located, so that the defect layer extends over the width of the second layer and over the whole width of the third layer formed as a source region. However, for the above described manufacturing or finalizing of the electrically insulating layer, a high temperature step has to be performed, by which undesired activation of the defects is introduced and thus, recombination centers are destroyed. Furthermore, it is difficult to make such a structure with the defect layer extending across the poly opening and under the source regions as disclosed in DE 102 61 424 B3. Such a device can have negative implications on the device safe operating area and on-state performance since it provides a high resistance path under the source regions which normally results in thyristor latch-up and device failure. This device can also negatively influence the MOS channel parameters and charge distribution near the IGBT cell.